DDR-SDRAMs need a refresh operation for reproducing stored information before the leakage of accumulated capacity's electric charge information causes data inversion. Further, adopted for DDR-SDRAMs is Dynamic On Die Termination by which a termination resistance provided in a data-related external interface circuit allows signal reflection at a device end to be suppressed readily to ensure the quality of waveforms required for high-speed data transfer; the resistance value is selectable. The value of the resistance selectable in Dynamic On Die Termination (also herein referred to as Dynamic ODT, simply) must be decided in consideration of its temperature characteristic and a source voltage, and therefore the arrangement which allows a calibrating operation for correcting the resistance value in Dynamic ODT to be performed is made.
Patent Document 1 has described a memory controller which issues a command to order a calibrating operation for correcting a resistance value associated with the Dynamic ODT.
Patent Document 2 has described a calibration circuit and a correction circuit according to Dynamic ODT in DDR-SDRAM.